AI-Optimized VLSI Architecture for Energy-Efficient and Sustainable IoT Systems

Shujaatali Badami

doi:10.1109/ICAIC67076.2026.11395694

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AI-driven silicon, 43% less power, 30% less delay.

Reinforcement learning, genetic algorithms and Bayesian optimisation steering Cadence and Synopsys synthesis flows toward power-delay sweet spots traditional VLSI tooling cannot reach.

Shujaatali Badami ·First author of 6 ·IEEE ICAIC · 2026 ·18 February 2026 ·~6 min read

At a glance

VenueIEEE ICAIC2026 (accepted)

Power saving43.3%vs conventional VLSI

Delay reduction29.7%critical path

Energy reduction52%end-to-end

ToolingCadence + Synopsysindustry-standard flow

Co-authors6 totalfirst author

DOI ↗ IEEE Xplore ↗ Cite All publications

Abstract, verbatim

The artificial intelligence and Internet of Things boom has created the necessity to implement energy-efficient hardware platforms capable of delivering smart computations in real-time at the network border. Traditional VLSI design tooling cannot generally implement sustainable IoT designs, as it cannot realise high performance and low power consumption simultaneously. This paper proposes an AI-Optimised VLSI Architecture, a design approach that uses machine-learning-based design-space exploration and provides adaptive power management and energy harvesting schemes. The framework applies reinforcement learning, genetic algorithms and Bayesian optimisation to optimise synthesis and layout parameters intelligently. According to Cadence and Synopsys design-tool simulations, the architecture achieves 43.3 percent power savings, 29.7 percent delay reduction and 52 percent energy reduction compared to conventional VLSI systems. The architecture incorporates dynamic voltage and frequency scaling, clock gating, and AI-based power gating.

01Why traditional VLSI tooling cannot get IoT right

The performance-per-watt envelope IoT now demands is not reachable with hand-tuned synthesis sweeps. Healthcare, smart cities, agricultural sensing, renewable-energy management, all of them want microcontroller-class power budgets at near-edge-server compute.

Traditional EDA flows were not designed for that. Their assumption is a designer iterating manually through a small parameter space. AI-driven design-space exploration replaces the iteration with policy learning over a far larger search space.

02The optimisation stack

Three optimisers, three roles:

Reinforcement learning for sequential synthesis-and-layout decisions where the action at each step constrains the next. Power-gating and clock-tree placement are the natural fits.
Genetic algorithms for global parameter sweeps where the loss landscape is bumpy and gradient-free methods earn their keep.
Bayesian optimisation for the expensive simulator-in-the-loop runs where every evaluation costs real wall-clock time and you need sample efficiency.

All three feed Cadence and Synopsys flows directly, which is the part that matters for adoption: nothing in the proposal asks the designer to leave their existing toolchain.

03What the numbers say

"43 percent power, 30 percent delay, 52 percent energy. Those are not paper-only numbers, they are industry-standard simulator outputs on industry-standard flows."

Plus the architecture-level moves: dynamic voltage and frequency scaling for active-mode efficiency, clock gating for switching-power reduction, AI-based power gating for leakage minimisation. Each compounds with the AI-driven synthesis-stage savings to extend device lifetime in energy-constrained IoT deployments.

04Where this fits in the stack

This paper is the silicon layer beneath the oneM2M wire format and the PQC-anchored metering framework. The same dollar of energy budget covers more compute when the silicon is AI-optimised; that is what makes residential-scale quantum-resilient IoT economically plausible.

FAQWhat people ask me about this paper

Q1Why not just use commercial AI-EDA products?

Commercial AI-EDA is closing in on these results, but the technique stack here is open and reproducible: published optimisation algorithms, standard simulators, no black-box vendor layer.

Q2Are the reported savings worst-case or best-case?

They are aggregate over the benchmark suite, not best-case cherry-picks. The paper reports the per-benchmark breakdown.

Q3How sensitive is the result to PDK choice?

The optimiser is PDK-agnostic; the absolute numbers shift with the technology node, but the relative gain over conventional flows is consistent.

Q4Does this require a custom RTL?

No. The framework wraps standard RTL flows; the AI lives in the synthesis-and-layout decision space, not in the RTL.

Q5What is the catch?

Wall-clock optimisation time. AI-driven exploration is slower per design than a single conventional run, but the resulting design is far better; the trade is engineering time for silicon energy, which is the right direction.

CITEHow to cite this paper

@inproceedings{badami2026vlsi,
  author    = {Shujaatali Badami and others},
  title     = {AI-Optimized VLSI Architecture for Energy-Efficient and Sustainable IoT Systems},
  booktitle = {IEEE ICAIC 2026},
  year      = {2026},
  publisher = {IEEE}
  doi       = {10.1109/ICAIC67076.2026.11395694}
}

S. Badami et al., "AI-Optimized VLSI Architecture for Energy-Efficient and Sustainable IoT Systems," in IEEE ICAIC 2026, 2026, doi: 10.1109/ICAIC67076.2026.11395694.

Badami, S., et al. (2026). AI-Optimized VLSI Architecture for Energy-Efficient and Sustainable IoT Systems. In IEEE ICAIC 2026. https://doi.org/10.1109/ICAIC67076.2026.11395694

TY  - CONF
AU  - Badami, Shujaatali
TI  - AI-Optimized VLSI Architecture for Energy-Efficient and Sustainable IoT Systems
T2  - IEEE ICAIC 2026
PB  - IEEE
PY  - 2026
DO  - 10.1109/ICAIC67076.2026.11395694
ER  -

At a glance

01Why traditional VLSI tooling cannot get IoT right

02The optimisation stack

03What the numbers say

04Where this fits in the stack

FAQWhat people ask me about this paper

CITEHow to cite this paper

SEE ALSORelated work in this portfolio

Quantum-resilient IoT energy metering

Lightweight oneM2M for IoT

AI-driven green cognitive radio